1. The Field of the Invention
The present invention relates to a method and a device for parallel control of two phase delay elements connected in series, two phase control signals for increasing or decreasing the phase delay of the two phase delay elements being generated as a function of the input signals and the output signals of the two phase delay elements.
2. The Relevant Technology
Methods and devices of this kind are used in particular in a Delay-Locked Loop (DLL) in which the phase delay of phase delay elements is controlled to match a certain reference value by means of a control process in order to generate at least one delay signal which is phase-delayed in a defined manner with respect to an input signal. An important component of this process is phase detection, by means of which the phase control signals for driving the phase delay elements are generated as a function of the actual phase delay of the phase delay elements. Two types of phase detection exist. The first type is binary phase detection, using an output signal of constant amplitude the polarity of which changes as a function of whether the phase difference at the input is positive or negative. The second type is linear phase detection, in which the amplitude of the output signal is proportional to the phase difference at the input. The second type is preferable in principle because it makes possible a rapid approach to the steady oscillating state in combination with stable, smooth behavior in the steady oscillating state itself, in which the phase difference at the input becomes very small.
There are, in principle, two methods by which linear phase detection can be realized. The first is based on a state machine with flip-flops as state storage devices, as are also used for a phase frequency detector in a Phase-Locked Loop (PLL). When this method is used, however, there is the fundamental problem with the DLL that, through an incorrect start condition or a missing signal during operation, the phase frequency detector can reach a state in which it supplies false signals, as a result of which the DLL seeks to move towards a different stable state than the one desired. Because only the delay is controlled in the DLL and not the frequency, as in the case of the PLL, a phase frequency detector of this type in a DLL cannot autonomously release itself from this state. Additional circuits are therefore needed to recognize such a state and make control interventions, necessitating a certain complexity and cost. An example of such a method is described in “CMOS DLL-based 2-V 3.2-ps jitter 1 GHz clock synthesizer and temperature-compensated tunable oscillator”, Foley, D. J., Flynn, M. P., Solid-State Circuits, IEEE Journal of, Vol. 36, No. 3, March 2001, pp. 417-423.
The second method for realizing linear phase detection consists in using only logic gates and no state storage devices. In a PLL, this method has the disadvantage that, unlike the phase frequency detector based on a state machine, it functions only for small frequency differences between the two input signals. In a DLL, by contrast, all signals always have the same frequency since in this case only the delay is controlled, so that a pure phase detector is sufficient. In this case, the realization using only logic gates without state storage devices has the advantage that false states cannot occur in the first place and the necessary additional cost of circuitry for recognition and correction is eliminated.
A phase detection system generally supplies two phase control signals, an up signal to increase the delay of the phase delay elements and a down signal to reduce the delay of the phase delay elements. As a rule, both signals act on a charge pump. This consists of switchable current sources which during the switched-on period apply a charge to a capacitor or drain it from same, thereby changing the control voltage for the phase delay elements. Because the current sources cannot switch on and off with unlimited speed and because it is nevertheless desired to control even very small phase differences, in the steady oscillating state both the up signal and the down signal are as a rule switched on simultaneously for a certain duration during each period. The difference between the two switched-on durations, which in principle can be as small as desired, then corresponds to the effective control signal.
An example of a phase detection system of this kind is described in “A dual-loop delay-locked loop using multiple voltage-controlled delay lines”, Yeon-Jae Jung, Seung-Wook Lee, Daeyun Shim, Wonchan Kim, Changhyun Kim, Soo-In Cho, Solid-State Circuits, IEEE Journal of, Vol. 36, No. 5, May 2001, pp. 784-791. Here, the up signal and the down signal are switched on simultaneously for one-eighth of the period duration in the steady oscillating state. Such a method is useful at relatively low frequencies in which this switched-on duration, which is short in relation to the period duration, is still sufficiently long not to cause problems through the limited switching on and off speed of the charge pump. A short switched-on duration also helps to save current if current flows in the charge pump only when the up signal or the down signal is switched on.